Formal Presentations

[1] “Adapting the RACER Architecture to Integrate Improved In-ReRAM Logic Primitives”, presented at the 15th Annual Non-Volatile Memories Workshop, Mar. 2023.

[2] “RACER: Bit-Pipelined Processing Using Memory”, presented at the 14th Annual Non-Volatile Memories
Workshop as finalist for the NVMW Memorable Paper Award, May, 2022.

[3] “RACER: Bit-Pipelined Processing Using Memory”, presented at the 54th IEEE/ACM International Symposium on Microarchitecture, Oct. 2021.

[4] “Energy Efficient Computation using RRAM for Compute in Memory”, presented at DSSC-WDC Fall Technical Review, Nov. 2020.

[5] “RACER: High-Efficiency Processing in RRAM Through Bit-Pipelining”, presented at IBM IEEE CAS/EDS AICompute Symposium, Oct. 2020.

[6] “Processing-In-Memory Architecture Using RRAM – Systems Considerations”, presented at DSSC West Coast Review, May 2020.

[7] “Graph Coloring with the Gunrock Framework”, presented at ECE Industrial Affiliate Conference, May 2019.

[8] “Towards Self-Driving Car: Pedestrian and Traffic Sign Detection”, presented at the Undergraduate Research Conference, Apr. 2018.

[9] “Towards Self-driving Car: Lane Line Detection and Control”, presented at the ECE Industrial Affiliate Conference, Apr. 2018.